library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity CPU is
    port (
        clk : in std_logic;
        reset : in std_logic;
        data : in std_logic_vector (7 downto 0);
        address : in std_logic_vector (7 downto 0);
        data_out : out std_logic_vector (7 downto 0)
    );
end CPU;

architecture arch of CPU is

    -- component RAM is
    --     port (
    --         clk : in std_logic;
    --         reset : in std_logic;
    --         data : in std_logic_vector (7 downto 0);
    --         address : in std_logic_vector (7 downto 0);
    --         data_out : out std_logic_vector (7 downto 0)
    --     );
    -- end component;

    component ALU is
        port (
            input1 : in std_logic_vector(7 downto 0);
            input2 : in std_logic_vector(7 downto 0);
            -- opcode : in std_logic_vector(7 downto 0);
            enable : in std_logic;
            output0 : out std_logic_vector(7 downto 0)
        );
    end component;

    component OPDECODER is
        port (
            opcode : in std_logic_vector(7 downto 0);
            en_add : out std_logic;
            en_store : out std_logic;
            en_load : out std_logic;
            en_jump : out std_logic;
            en_jneg : out std_logic
        );
    end component OPDECODER;

begin

end arch; -- arch
